Energy consumption of computer based equipment has been a general concern of computer designers. This is particularly true for mobile computing devices that are powered by batteries. More particularly, power consumption is a primary concern of conventional design of central processing units (CPUs). This is particularly true for consumer electronics devices such as MP3 players, MPEG players, cell phones, personal digital assistants (PDAs), laptop computers, and more. On-chip cache memory is the primary source of power consumption since up to 80% of on-chip transistors are devoted to cache memories. Existing technologies such as such as filter cache, frequent value data cache, reconfigurable cache, and data compressions seek to reduce the power consumption of cache memories.
Filter cache technologies employ an unusually small level 1 (L1) cache to perform most of caching activities while using a large level two (L2) cache to reduce penalty caused by high miss rate of such small L1 cache. The approach effectively trades performance for power consumption by filtering cache references. The frequent value data cache technique exploits the data locality property that a few values (4 to 128) are used very frequently by CPU. By storing these values in a register file indexed by a few encoded bits in the cache, they are able to reduce power consumption of cache memories greatly. Reconfigurable cache designs seek to adapt the cache configuration to different applications so that the cache can be better utilized. Data compressions in cache is aimed at reducing required cache size yet hold the same amount of data or enlarge cache capacity to hold large amount of data. Another approach reduces energy consumption through dynamic zero compression such that a large portion of cached data are zeros. Instead of accessing those zeros in its original form, they use one bit for each zero bytes. With only 2 additional FO4 gate delays for each read access, they are able to reduce total data cache energy by around 26% and instruction cache by around 10%.
Such existing technologies, however, are believed to provide only incremental improvement based on existing cache designs. There remains a need for a cache architecture that requires minimum power consumption.